Semiconductor devices known as charge compensation or super junction (SJ) semiconductor devices, for example SJ insulated gate field effect transistors (SJ IGFETs) are based on mutual space charge compensation of n- and p-doped regions in a semiconductor substrate allowing for an improved trade-off between area-specific on-state resistance Ron×A and breakdown voltage Vbr between load terminals such as source and drain. Performance of charge compensation of SJ semiconductor devices depends on a lateral or horizontal charge balance between the n-doped and p-doped regions. Process tolerances lead to deviations of a target charge balance, i.e. to a de-tuning of a desired degree of charge balance that may result in an undesirable decrease of device performance such as a reduction in a source to drain breakdown voltage.
It is desirable to improve the trade-off between the area-specific on-state resistance and the blocking voltage of a super junction semiconductor device and to reduce the impact of process tolerances on this trade-off.